As we know that RD (Read) is a control signal. Because this signal is used both for reading memory and for reading an input device, it is necessary to generate two different Read signal : one for memory read control signal and another for input read control signal. Similarly, two separate Write signal must be generated.
Above Figure shows that four different control signals are generated by combining the signals RD, WR and IO/M. The signal IO/M goes low for the memory operation. This signal is ANDed with RD and WR signals by using bubbled input NAND gates as shown in figure.
When both input signals go low, the outputs of the gates go low and generate MEMRD (Memory Read) and MEMWR ( Memory Write) control signals. When the IO/M signal goes high, it indicates the pehriperal I/O. Figure shows the generation of IORD (I/O Read) and IOWR (I/O Write) control signals.
CLOCK GENERATION METHOD IN 8085
The 8085 clock frequency can be generated by a crystal, an LC tuned circuit, or an external clock circuit. The frequency at X1, X2, is divided by 2 internally. This means that in order to obtain 3.03 MHz, a clock source of 6.06 MHz must be connect to X1 and X2. For crystal with less than 4 MHz, a capacitor of 20 pF should be connected between X2 and a ground to ensure the starting up of the crystal at the right frequency.
Second method of generating clock signal is using a parallel-resonant LC circuit. As shown in igure below parallel LC circuit can be used as the frequency source for the 8085. The values of L and C can be chosen using the following formula.
To minimize variations in frequency, it is recommended that a value for C should be chosen as twice that of Cin or 30 pf. The use of an LC circuit is not recommended for external frequency higher than approximately 5 MHz.
An RC circuit may also be used as the clock source for the 8085 if an accurate clock frequency is of no concern. Its advantage is the low component cost. Above figure shows a clock circuit for generating an approximate external frequency of 3 MHz. Note that frequencies greatly higher or lower than 3 MHz should not be attempted on this circuit.