Pin Configuration of 8085

Microprocessor Pin Description – 8085

In this article we will discuss 8085 microprocessor pin description. 8085 Microprocessor is a 40 pin IC which operates on +5 volt power supply and 3MHz frequency. These 40 pins are divided into six groups according to their functions. These groups are:

  • Frequency and power supply signals
  • Higher order address bus
  • Multiplexed address/data bus
  • Control and status signals
  • Serial IO signals
  • Externally or peripheral initiated signals.
Pin Configuration of 8085
Pin Configuration of 8085

These pin configuration of 8085 microprocessor is shown in figure below.

Group 1: Power Supply and Frequency Signals

X1, X2 (input) Microprocessor Pin

These are the two input lines across which a Crystal or R/C oscillator circuit is connected. It is to provide the required clock frequency to the microprocessor. The frequency generated by the oscillator is divided by 2 to give the internal operating frequency of the microprocessor. The input frequency is divided by 2 because the frequency is applied to the system through T flip flop. T flip flop divides the incoming frequency by 2 (as shown in Figure below).

INTERNAL CLOCK of microprocessor
INTERNAL CLOCK of microprocessor
  • Vcc – +5 volt supply
  • Vss – Ground reference.

Group 2: Higher Order Address Bus (Output) (A8-A15)

Instead of having 24 pins for address and data lines, 8085 has only 16 pins. Out of the 16 pins 8 pins are used to carry the higher order address and the other 8 pins are multiplexed to carry the address as well as the data. This multiplexing is done to keep the number of pin as minimum as possible.

The  most significant 8 bits of the memory address or the 8 bits of the I/O address is carried by these lines. These lines are tri-stated during Hold and Halt modes.

Group 3: Multiplexed Address/Data Bus (AD0-AD7)

The 8085 microprocessor uses a multiplexed data bus. These lines are time multiplexed with the lower 8-lines of the address bus. Lower 8-bits of the memory address or I/O address appear on the bus during the T1 state of a machine cycle. It then becomes the data bus during the second and the third clock cycles. These lines are tristated during Hold and Halt modes.

Group 4: Control and Status Signal

ALE (Address latch enable) (output)

ALE as its name suggest, enables the address latch to store the address during the demultiplexing operation. It occurs during the first T state of every machine cycle. Whenever microprocessor sends a valid address on the multiplexed lines, it also make the ALE signal high. This microprocessor pin also uses to strobe the status information. ALE is never tristated.

RD (read) (output)

Read is an active low output control signal. When this signal is low, it indicates that the microprocessor wants to read a data either from memory or IO device. Microprocessor activates this signal during the T2 state of the machine cycle as in this T state, the data bus is ready to carry the data. The read signal is tristated during Hold and Halt modes.

WR (write) (output)

Write is an active low output control signal. When this signal is low, it indicates that the microprocessor wants to write a data either into memory or IO device. Microprocessor activates this signal during the T state of the machine cycle as in this T state, the data bus is ready to carry the data. The write signal is tristated during Hold and Halt modes.


The Read and Write signals indicates that the microprocessor wants to read or write a data but do not specify from where this read or write operation will take place. This is indicated by IO/M signal. When this signal is low, it means a read or write operation will take place from/to memory. When this signal is high, it means the operation is with reference to IO. This signal is tristated during Hold and Halt modes.

S0 S1 (Status signal) (output)

These are the two data bus status signals. The four combinations of these signals gives the information of what the microprocessor is doing or the encoded status of the bus cycle.

Encoding of status signal in microprocessor
Encoding of status signal in microprocessor

Group 5: Serial IO Signal

SID (input)

Serial input data line (SID). This line is used in serial data communication. Through this pin, the serial data is received by the processor. The data on this line is loaded into eight bit accumulator bit whenever a RIM instruction is executed. Figure shows the SID operation.

Serial Input Data Line OPERATIONS
Serial Input Data Line Operations

SOD (output)

Serial output data line. This line is used in serial data communication. Through this pin the serial data is transmitted by the processor. The Serial output data line (SOD) is set or reset as specified by the SIM instruction. Figure shows the SOD operation

Serial output Data Line OPERATIONS
Serial output Data Line Operations

Group 6: Externally or Peripheral initiated Signals

TRAP (Input)

Trap is a non-maskable interrupt which have the highest priority. This microprocessor pin is recognized at the same time as INTR. This interrupt cannot be masked or disabled. This is a vectored interrupt. It is edge as well as level triggered.

RST 5.5, RST 6.5, RST 7.5: RESTART interrupt (inputs)

These three microprocessor pins have the same timing as INTR except they cause an internal RESTART to be automatically inserted. These interrupts are immaskable. The mask can be set to any of these interrupts by SIM instruction.

  • RST7.5 has the highest priority and it is edge triggered.
  • RST6.5 is level triggered.
  • RST5.5 has the lowest priority and it is edge triggered.

The priority of above interrupts is ordered as shown. These interrupt pins have a higher priority than the INTR.

INTR (interrupt request) (input)

INTR is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of an instruction cycle. When it is active, the Program Counter (PC) will stop incremented and an interrupt acknowledge signal is issued by the processor.

During this INTA cycle, a RESTART or CALL instruction can be inserted to transfer the control to the interrupt service routine (ISR). The INTR is enabled and disabled by the software instructions EI (enable interrupt) and DI (disable interrupt). It is also disabled by Reset and immediately after an interrupt is accepted.

INTA (interrupt acknowledge) (output)

This signal is generated by microprocessor in response to the INTR. When microprocessor accepts the INTR, it executes an INTA machine cycle. This cycle is exactly same as that of read cycle except that instead of RD signal, microprocessor sends the INTA in the T2 and T3 state. INTA can be used to activate 8259 Interrupt chip or some other interrupt port

READY (input)

This signal is used to synchronize the slower peripherals with microprocessor. If “Ready” pin is high during a read or write cycle, then it indicates that the memory or peripheral is ready to send or receive data. If “Ready” pin is low, then the CPU will wait for “Ready” to go high before completing the read or write cycle.

For example, if microprocessor is interfaced with a slower output peripheral device, the device will send logic 1 on the READY pin. On receiving the “READY” signal microprocessor will release the data and then enter into the wait state till the next time microprocessor receive the signal on READY.

HOLD (hold request) (input)

HOLD is bus request from a competent bus master. Whenever a competent bus master like DMAC (Direct memory access controller) wants to transfer data between memory and the IO it sends a request on the HOLD pin of the microprocessor. On receiving the Hold request signal the microprocessor suspends its current operation and relinquishes the buses as s the completion of the current machine cycle.


Internal processing can continue. The processor regains the control of the buses when the Hold request is dropped by the DMAC. When the Hold is acknowledged, the Address, Data, RD, WR’, and IO/M lines are tristated. This signal is polled by the microprocessor in the last T state of every machine cycle. Above Figure shows the HOLD operation.

HLDA: HOLD Acknowledge (output)

On receiving the HOLD request, the microprocessor completes the current machine cycle and then suspends its operation, release the buses and sends a HOLD acknowledge signal to the DMAC. HLDA goes low after the Hold request is dropped. The microprocessor takes the buses one half clock cycle after HLDA goes low.

RESET IN (input)

This signal is used to reset the processor. This microprocessor pin is one of the important pin of 8085. When microprocessor receives a signal on this pin it clears the Program Counter and resets the Interrupt Enable and HLDA Flip-flop. Except the Instruction register, all the general purpose data registers and the flag register remain unaffected by the Reset signal. The microprocessor is held in the reset condition as long as Reset is applied.

RESET OUT (output)

This signal is used by microprocessor to reset its peripheral devices. It can be used as a system RESET. This signal is synchronized to the processor.


Clock output is used as a system clock when a crystal or R/C network is used as an input to CPU. The period of clock is twice the X1 X2 input period.

Read Also: Microprocessor Introduction
8085 microprocessor Architecture

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